The Role:
The Design Technology Pathfinding (DTP) organization in Design Enabling (DE) is chartered to identify and drive key strategic initiatives in the pathfinding of future technologies, as a holistic Design co-optimization across the Product stack from System architecture to silicon as we extend DTCO to STCO (System Technology Co-Optimization). The job requires partnering and leveraging domain experts across Intel and the EDA Eco-System.
Your responsibilities may include, but not be limited to:
- Establish 3DIC Test Cases across market segments for technology definition and test chip certification
- Development of 3DIC construction and validation methodology. Evaluation and feedback of 3D-IC TFM and EDA capabilities
- Design analysis and feedback for 3D silicon and packaging technologies development
- Collaboration with the different Product teams to identify critical product characteristics and target setting requirements.
- Circuit Design analysis and design optimization of 3D advanced silicon/package technology features to enable product differentiation
The future of Moore's Law: 3D-IC
https://www.intel.com/content/www/us/en/newsroom/opinion/moore-law-now-and-in-the-future.htmlhttps://www.zdnet.com/paid-content/article/moores-law-under-the-microscope-intel-advances-transistor-technology/https://www.tomshardware.com/news/intel-teases-falcon-shores-xpu
This is an entry level position and compensation will be given accordingly.
#DesignEnablement
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences.
Minimum Qualifications:
Candidate must possess a PhD degree with 1+ years of experience in Electrical and Computer Engineering or related field.
1+ years of experience in the following:
- VLSI Design, Digital Design.
- Experience driving Physical Design place and route Synopsys/Cadence tools, design reference/sign-off flows in advanced technologies.
- Understanding of design methodology and tools features for IP/chip design.
- Scripting skills using a programming language such Python, TCL.
- Circuit design and silicon technology. Design challenges in advanced technologies.
Preferred qualifications:
2+ years of experience in the following:
- Computer Architecture.
- 3D-IC Silicon and packaging technologies.
- Machine Learning.
Annual Salary Range for jobs which could be performed in the US $123,419.00-$185,123.00
*Salary range dependent on a number of factors including location and experienceWorking ModelThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.