Job Description

Candidate will be joining an expanding high speed IO design team involved in design and development of next Gen memory interface PHY on cutting-edge process nodes.
Responsibility will primarily include ownership of various task involves : circuit design, validation, layout review, mixed signal validation, behavioral modelling and reliability validation.
Candidate will also be responsible for contributing to package and platform design guideline development.

Qualifications

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Candidate should possess 3+ year of experience with at least a Master degree in Electrical Engineering or equivalent.Strong fundamentals of CMOS design, RC circuits, high speed circuit design concept are a must for this roleCandidate should have experience of designing high speed IO circuits (SerDes, LPDDR, DDR, HBM) such as transmitter, receiver, clocking, PLL, DLL etc.

Added advantage

Exposure to high speed digital circuit design and analysis with timing and flow closure.Digitally assisted analog circuit and techniques.Experience with tools like Spectre, PrimeSim, HSPICE , Virtuoso, ADE and Custom Compiler or equivalent schematic and layout editor tools, Knowledge of DRC, LVS, and post-layout extraction toolsFamiliarity with Simulation tools (EMX, HFSS, Helic, Momentum) to execute SI-PI simulations is required.Experience with performing measurement, and correlating measurements to simulations.Experience with modeling and simulation of high-speed interface interconnects/channelExcellent analytical and problem-solving skills
Inside this Business Group
In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.


Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.


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Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.