At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.
We are hiring highly competent technical experts for our next generation memory interface PHY IPs (DDR/HBM/UCIe).
Responsibilities:Lead next generation high-speed memory interface PHY IPs (DDR/HBM/UCIe) developmentDrive innovation towards high-speed IO designs for memory interface PHY IP in CMOS/FinFET/GAACollaborate with cross-functional teams across globe Requirements-Qualification: BTech/MTechSkills/Experience: 8-15 yearsProficient in analog design fundamentals, device physics Expert in high-speed IO designs in advanced technologiesKnowledge of JEDEC requirements for memory interfaces and standards would be a plusGood understanding of ESD and reliability conceptsFamiliarity with signal integrity and/or power integrity is a plusDrive design teams to deliver best quality productsExcellent written, verbal communication and interpersonal skills Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, or disability.