Job Description & Responsibilities 
Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything―where devices are getting smarter, everything’s connected, and everything must be secure.
 
Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them. Synopsys is at the forefront of Smart, Secure Everything with the world’s most advanced tools for silicon chip design, verification, IP integration, and application security testing. Our technology helps customers innovate from Silicon to Software, so they can deliver Smart, Secure Everything.
 
The broad DesignWare IP portfolio includes logic libraries, embedded memories, embedded test, analog IP, interface IP, security IP, embedded processors, and subsystems. To accelerate prototyping, software development and integration of IP into SoCs, Synopsys' IP Accelerated initiative offers IP Prototyping Kits and IP subsystems. Our extensive investment in IP quality, comprehensive technical support and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market. At Synopsys, you will have the opportunity to find the perfect blend of our strong EDA presence and our broad IP portfolio.
  
Our Solution Group's Central IP team in Hyderabad India is looking for an enthusiastic individual to join our team. You will be working with a cross functional team of analog and mixed signal circuit designers from a wide variety of backgrounds on design and methodology. This position requires hands on experience with transistor level simulations, reliability analysis, static timing analysis (STA) tools, a vast knowledge of mixed signal circuit design principles, a deep understanding of silicon IP release requirements, strong scripting skills to automate flows and the ability to lead and train junior engineers to become experts with new methodologies.
 
Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or similar technical fieldBSEE degree and 15-20 years of experience in IC design, or MSEE (or PhD) with 12-15 years of experience.Extensive knowledge of Analog & Mixed-Signal circuit designDeep design experience in high speed PHY such as SERDES, DDR or HBMProficiency with spice simulators including HSPICE, PrimeSim/FineSim and XADeep knowledge on DC/AC/Transient, Cross corners PVT, Static & Dynamic CCK, Equivalency checks, Aging, EMIR/SHE Reliability analysis, MonteCarlo simulationsExperience with STA and cell characterization such as Nanotime, Primetime, SiliconSmartUnderstanding of behavioral Verilog models & experience in SystemVerilog for AMS circuits Knowledge in Perforce and/or regressions is a plusPrior experience on products/test chips bring up, lab debug and simulations to silicon correlation is highly desirable Prior working knowledge in the SERDES/DDR PHY level timing closure, implementation would be an added advantageCandidate with Machine Learning paradigms/techniques understandings with knowledge of applying it in modeling, circuit design flow & simulations is desirable