Analog Design, Staff Engineer
 
Qualification:
Experience Required: 5+ years
Education: Btech/Mtech/Phd. Electronics/Electrical engineering
 
Skills/Experience:
- Recent experience delivering High speed IO design including Latest DDR/HBM I/O designs for low power wireless devices.
- Solid understanding of related CMOS and FinFET process technology  and associated issues in 28nm and smaller.
- I/O design methodology & flow, Calibration, JTAG design requirements, understanding of analog circuitry, good understanding of ESD and LU based design concepts. Good understanding on the reliability aspects of designs such as Ageing and MC simulations.
- Familiarity with ASIC flow: Synopsys libraries, LEF generation, Place & Route & understanding of top level verification flow.
- DDR/LPDDR/HBM design experience.
- Good Understanding of the DDR Timing, ODT and SDRAM functionality.
- Familiarity with: JEDEC requirements for DDR interfaces & standards; Power & Signal Integrity.
- Additional preferred experience in design and development of GPIO's, Special high speed IO's such as LVDS, USB, MIPI, DigRf, PLL's, ADC, etc
- Ability to foster accountability and ownership through hands-on technical leadership.
- Excellent written and verbal communication skills in interactions with customers, and internal development teams.
- 5+ year's CMOS/FinFET IO and Mixed Signal circuit development expertise
 
Responsibilities:
- DDR/LPDDR/HBM I/O Circuit and layout design including GPIO and Special IO’s.
- Provide subject matter expertise and technical leadership in design of high speed I/Os such as DDR.
- Work with DDR/HBM PHY team, package engineers and system engineers to meet design specifications.