Kforce has a client that is seeking an Analog IC Layout Engineer in Austin, TX. The IC Layout Design Engineer will work closely with circuit designers to generate topological layouts of high-performance, cutting-edge semiconductor products. Responsibilities: * Work closely with circuit designers to complete the physical layout and verification of high-performance analog/mixed-signal CMOS Integrated Circuits using Cadence Virtuoso XL Layout and PVS Verification tools in FinFET technologies * As an Analog IC Layout Engineer, you will use problem solving skills, experience, and creativity to layout circuits that meet size, schedule, and performance specifications while meeting FinFET technology rules * Run physical design verification tools to debug, improve, and verify layout blocks * Collaborate with fellow team members on continuous improvement opportunities in the flow, layout techniques, and design methodologies