Description:
 
As the SoC are getting complex and thus includes complex verification methodologies and challenges. To address these needs   Synopsys Verification Continuum™ platform provides VCS® simulation, Verdi® debug, SpyGlass® static, VC Formal, fastest emulation system and Prototyping.  

Synopsys ZeBu® emulation system delivers the performance needed to make verification teams and software developers working on the most advanced chips successful. ZeBu emulation systems are modular, allowing users to deploy the capacity needed in a scalable and easily extensible fashion.

Synopsys ZeBu EP is the most scalable unified hardware platform for emulation and prototyping. It leads the industry with the highest performance and capacity scaling to validate long software workloads for billion+ gate designs.   
 
Responsibilities
 
You will be working as Applications Engineer, Staff Engineer in Synopsys’s System Design Group, you will be responsible for pre-sale and post-sale support of Synopsys’s Zebu EP based emulation platforms. You will have the opportunity to work with customers to help successfully emulation based verification for their multi-million gate ASIC designs.
 
This job provides an opportunity for you to be involved in highly technical challenging evaluations of Synopsys’s Zebu emulation platforms.  You will part of Zebu Application Engineering team who act as experts of our emulation products in Synopsys. The responsibility includes supporting Synopsys customers for various product evaluations and post-sale support.  To help with Pre-sales activity or product deployments or support issues, you may be required to travel to work in customer sites for specific periods of time.  You will be required to publish solvent articles and developing application notes based on customer experiences.  You will be responsible for developing training materials required for the customers.   You are also expected to contribute improving the Quality of Results in the tools and propose new flows and features.
 
 
Minimum Requirements
 
BS with minimum 5 years of relevant experience or MS with minimum 3 years of experience.   
 
Preferred Skills 
Must have hands on experience with design verification flow with simulation and emulation based flow.
Experience with design, verification, post silicon bring-up and validation
Knowledge of Digital Design, VHDL/Verilog/SystemVerilog , Synthesis , Simulation and FPGA architectures such as Xilinx Ultrascale devices.
Must have good knowledge on FPGA-based design debug and handle complex timing constraints for FPGA designs
Must have good knowledge scripting language such as TCL/Python
Knowledge of ARM buses, display controller/interface, industry standards (MIPI, HDMI, USB, PCIe, SATA etc.) is a plus
 
Our Silicon Design & Verification business is all about building high-performance silicon chips—faster. We’re the world’s leading provider of solutions for designing and verifying advanced silicon chips. And we design the next-generation processes and models needed to manufacture those chips. We enable our customers to optimize chips for power, cost, and performance—eliminating months off their project schedules.
 
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
 
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.