The application window is expected to close on 12/23/2024

This role can sit in our Milpitas/San Jose office location, or remotely in Austin, TX.

What You'll Do:

It used to be that high-speed packet forwarding was performed in dedicated ASIC designs. These days we are looking to make those ASICs more general and programmable. Cisco Common ASIC Group is looking for a Senior ASIC Verification Engineer to drive existing projects and engage in new development of our next-generation switching systems.

As part of the ASIC team, you will be developing the ASICs at the heart of each of these switch products. There are only a very few teams worldwide that implement such devices. Every time you access the Internet, chances are, your data's been through one of our switches.

Who You'll Work With:

You will work with Cisco’s best-in-class switching solution team. Our team is responsible for driving integration of the Nexus systems and ACI with software, including OpenStack, Docker, and Open vSwitch, to help our customers build multitenant clouds.

Who You Are:

You are a talented, motivated ASIC verification engineer to join the team and contribute to the verification of very complex ASICs. You will have a Design Verification background, and hands-on experience in System Verilog and UVM methodology, with in-depth knowledge of C++, scripting, as well as ASIC design and verification flow.

You’ll be part of the Cisco Common ASIC Group, focusing on developing and upgrading various test benches and contributing to different aspects of verification infrastructure.

You will collaborate closely with the design team and the hardware team to verify the ASIC in simulation, in emulation, and during ASIC bring-up.

Responsibilities Include:

Create block level test benches including components like drivers/monitors/sequencesMaintaining existing test benches for block level and/or cluster levelUpgrading test benches to accommodate new featuresEnd-to-end verification of various design blocksDeveloping test plans, cover pointsUpgrading/updating configuration/reset sequences (APIs)Collaboration with designers/verification engineers to perform cross-block verificationWriting tests, and debugging regressionsContributing to top level verificationBe a part of emulation testing efforts

Education and Experience Required:

Master’s degree in EE (Electrical & Electronics) or CE (Computer Engineering) with 2+ YoE in Design VerificationBachelor’s degree in EE or CE and 3+ YoE in Design Verification

Knowledge and Skills:

Required Skills: Hands-on and deep understanding of System Verilog and UVM methodologyAbility to write System Verilog constraints, construct testbench including scoreboard, agents, sequencers, and monitorsAbility to debug issues independentlyProficient in functional coverage and constrained random DV environmentsGood written and verbal communication skillsCollaborative and team-focused, with the drive to learn and grow Nice to have Skills: Basic scripting experience (Python, Perl, shell programming) Nice to have C, C++ programming and debugging skills

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