The application window is expected to close on 3/28/2025

Meet The Team:

 

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. 

  

Your Impact:

You will be in the Silicon One development organization as an ASIC DFT Product Lead in San Jose, CA with a primary focus on Design-for-Test and Product qualification activities

Key Responsibilities:  

 

Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs. Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL, post silicon validation flows. Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies. The job requires the candidate to have the ability to craft solutions and drive cross functional and external vendor interactions

Minimum Qualifications: 

Master’s Degree in Electrical or Computer Engineering required with at least 12 years of experience. 
Prior experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. 
Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime 
Prior experience with Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687 
Prior experience with full chip DFT architecture, hierarchical testing, and high speed interface tests

Preferred Qualifications: 

Verilog design experience – developing custom DFT logic & IP integration; Experience leveraging functional verification routines for DFT DV.DFT CAD development & EDA interactions – Test Architecture, Methodology and Infrastructure Background in Test Static Timing Analysis with Test Constraint signoff ownership a plus..Past experience with Post silicon validation using DFT patterns and product engineering.Have participated  in multiple tapeouts and silicon bringup activities.