ASIC Digital Design, Manager
Synopsys (formerly Synfora)
The selected candidate will be part of the DesignWare IP R&D team at Synopsys. the opening is for a Design Manager. The candidate will be expected to specify, design/architect and manage the development for the synthesizable DesignWare cores. Candidate will lead a team of around 5 to 10 engineers and will work closely with a broader global team of RTL designers, Architects and Verification Engineers.
The candidate will be part of the Solutions Group, India. This is a Technical Manager role and offers challenges to work in a multi-site environment with good exposure to different people and skillset development. The position offers to work on NextGen DesignWare IPs and with good learning and growth opportunities.
Key Qualification:BS/MS in EE/EC/VLSI stream with 8-15 years of relevant experience in the design of IP cores and/or SOCExperience in leading a team of engineers.Hands on experience on design and verification of complex designs at IP or/and SoC level.Strong knowledge of Verilog/System Verilog language is needed.Hands-on experience with Synthesis, Timing Closure, DFT, Static Checks (CDC, RDC, LINT) Tools and Low Power FlowsHands-on experience in Assertion based Formal Property Verification is a definite plus.Experience in Interface protocols like USB/PCIE/ENET/DDR is desirable.Exposure to IP design and verification processes including usage of VIPs is desirable.Exposure to Perl/Python based automation is preferred.Good communication skills, debug, and problem solving skills, and should be self motivatedPreferred Experience:Be a strong team leader, motivator with a go-getter attitude.Be a technical contributor in the Design and Verification Tasks Creates deliverables which do not require close review or supervision by the senior management.Understand needs of Project milestones and align the team tasks accordingly. Be able to study the coverage metrics and improve them with definition of additional test casesFamiliarity with HDLs such as Verilog and scripting languages such as shell/Perl/Python etc. is highly desirableWorks in a project and team oriented environment with teams spread across multiple sites, worldwide.Soft Skills:Good team player with inter personal and communication skills.High levels of motivation and self-propulsion.Business Area Description:
Our Silicon DV business is all about building high performance silicon chips faster. We're the world's leading provider of solutions for designing and verifying advanced Silicon chips. We design the NextGen processes and models needed to manufacture those chips. We enable our customers to optimize chips for power, cost and performance.
About Synopsys:
At Synopsys, we're at the hear of the Innovations that change the way we work and play. Our chips are everywhere (Self driving Cars, AI, HPCs, 5G, IOT, etc.) enabling the Era of Smart Everything. We're powering it all with the world's most advanced technologies for chip design and SW security.
EEO:
Inclusion & Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status or disability.
The candidate will be part of the Solutions Group, India. This is a Technical Manager role and offers challenges to work in a multi-site environment with good exposure to different people and skillset development. The position offers to work on NextGen DesignWare IPs and with good learning and growth opportunities.
Key Qualification:BS/MS in EE/EC/VLSI stream with 8-15 years of relevant experience in the design of IP cores and/or SOCExperience in leading a team of engineers.Hands on experience on design and verification of complex designs at IP or/and SoC level.Strong knowledge of Verilog/System Verilog language is needed.Hands-on experience with Synthesis, Timing Closure, DFT, Static Checks (CDC, RDC, LINT) Tools and Low Power FlowsHands-on experience in Assertion based Formal Property Verification is a definite plus.Experience in Interface protocols like USB/PCIE/ENET/DDR is desirable.Exposure to IP design and verification processes including usage of VIPs is desirable.Exposure to Perl/Python based automation is preferred.Good communication skills, debug, and problem solving skills, and should be self motivatedPreferred Experience:Be a strong team leader, motivator with a go-getter attitude.Be a technical contributor in the Design and Verification Tasks Creates deliverables which do not require close review or supervision by the senior management.Understand needs of Project milestones and align the team tasks accordingly. Be able to study the coverage metrics and improve them with definition of additional test casesFamiliarity with HDLs such as Verilog and scripting languages such as shell/Perl/Python etc. is highly desirableWorks in a project and team oriented environment with teams spread across multiple sites, worldwide.Soft Skills:Good team player with inter personal and communication skills.High levels of motivation and self-propulsion.Business Area Description:
Our Silicon DV business is all about building high performance silicon chips faster. We're the world's leading provider of solutions for designing and verifying advanced Silicon chips. We design the NextGen processes and models needed to manufacture those chips. We enable our customers to optimize chips for power, cost and performance.
About Synopsys:
At Synopsys, we're at the hear of the Innovations that change the way we work and play. Our chips are everywhere (Self driving Cars, AI, HPCs, 5G, IOT, etc.) enabling the Era of Smart Everything. We're powering it all with the world's most advanced technologies for chip design and SW security.
EEO:
Inclusion & Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status or disability.
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