Job Description and Requirements
 
Job Description
The candidate will be part of the DesignWare IP Design R&D team at Synopsys. He/she will be expected to specify, design/architect and implement state-of-the-art RTL for the DesignWare family of synthesizable cores and perform Design tasks for the IP cores. He/she will work closely with RTL verification and be part of a global team of expert Design Engineers. He/she will also work closely with other IP design teams and IP support team.
Job role will have a responsibility of Functional specification development, Micro architecture development, RTL development and unit level testing, RTL reviews, exercising the RTL with various design flows, debugging and supporting the verification team on meeting the coverage metrics.
 
Requirements:
Must have BSEE in EE with 2+ years of relevant experience or MSEE with 1+ year of relevant experience in the following areas:
- Must have experience in developing Functional specification, Architecture, micro architecture and HDL (Verilog) based implementation.
- Must have strong HDL coding skills for RTL development, must have experience in developing RTL code which is multi-clock domain, complex FSM, Data path and control path implementation.
- Expertise in Design tool flows such as Spyglass, VC Spyglass, STA, DC, Fusion Compiler, Formality is a plus.
- Familiarity with scripting languages such as Perl, TCL, Python is a plus.
- Exposure to IP design processes and high speed protocols such as USB/PCIe/DDR is an added advantage.
- Good written and oral communication skills. Demonstrates good analysis, debug and problem solving skills and shows high levels of initiative.
 
Location: Bengaluru, India
 
Inclusion and Diversity is important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.