The selected candidate will be a key member of the Synopsys DesignWare ARC Processor hardware verification team.
Responsibility includes ownership of complete verification process including creation of test plans, development of testbenches, creation of tests – both directed and random, functional coverage modelling and analysis, code coverage analysis, debugging and resolving mismatches between design and C-model, integration of third party and internal verification IP, regression management, review and improvement of verification test suites.
Candidate should be able to lead verification team and provide guidance and mentorship. Candidate should be able to represent team in various forums with global audience.

Job Requirements:Bachelor’s degree in engineering is required as a minimum from a reputed collegeMinimum eight years of experience in digital front end functional verificationMicroprocessor architecture knowledgeHDL and Verification languages: SystemVerilog, VerilogVerification methodologies: UVM/OVMProgramming skills: C, assembly, Perl, makefile generation Tools: RTL Simulators, eg VCS.Experience in technical leadership of a verification teamExperience in working with global teamsWritten and Verbal communication skills: Creation, modification and review of test documentation: testplans, procedures, test scenarios, test reportsAbility to represent verification team in global platforms Analytical skills:Analysis of verification requirements to close out on product releaseAbility to analyze test results and provide reportsProvide guidance to team based on result analysisSelf-motivated team player able to thrive in a fast-paced engineering environmentInspire team for technical excellence