Key responsibilities:Identify verification environment requirements from its various sources (Specifications, Design functionality, Interfaces, etc …)Generate verification test plan, verification environment documentation and test environment usage documentationDefine, develop, and verify complex UVM verification environmentsEvaluates and exercises various aspects of the development flow. May include such items as Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modelling, and verification coverage metrics (functional coverage and code coverage)Identify design problems, possible corrective actions and/or inconsistencies on documented functionalityKey QualificationsProven desire to learn and explore new state of the art technologiesDemonstrate good written and spoken English communication skillsDemonstrate good review and problem-solving skillsKnowledgeable with Verilog, VHDL and/or SystemVerilogKnowledgeable with scripting languages (BASH/TCSH/PERL/PYTHON/TCL) is a plusUnderstanding of verification methodology such as UVM is a plusGood organization and communication skills8+ years of relevant experience