ASIC Digital Design, Sr Staff Engineer
Synopsys (formerly Synfora)
Job Overview
Synopsys is a leading provider of high-quality, silicon-proven IP solutions for SoC designs. The broad DesignWare IP portfolio includes logic libraries, embedded memories, embedded test, analog IP, wired and wireless interface IP, security IP, embedded processors and subsystems. Synopsys DesignWare SERDES PHY is uniquely positioned in the industry as one of the most complex and high performing IP, in terms of interface, feature support as well as deployment across a wide spectrum of customer products. We are looking for a full time IP RTL Design position to work on our High Speed SERDES PHY development.
Location: Hyderabad
Preferred Qualifications
Key Responsibilities
Understanding IP SpecificationsDefines and develop micro-architectureRTL Design using Verilog/System VerilogInteracting with cross functional teams to resolve the issues in creative wayHelping verification team to debug the issueRunning ASIC development tools including Lint and CDCGuides junior peers with aspects of their job
Confirm your E-mail: Send Email
All Jobs from Synopsys (formerly Synfora)