At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars, Artificial Intelligence, The cloud, 5G, The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities, meet unique performance, power, and size requirements of their target applications and get differentiated products to market quickly with reduced risk. 

Implementation Engineer

Seeking a highly motivated and innovative physical implementation engineer with theoretical background in memory controller implementation. The successful candidate will be part of de Designware IP High Bandwidth Memory (HBM) Controller R&D team (or similar protocols), and will perform a key role in linking the front-end RTL design with the back-end physical implementation design.  

The successful candidate will drive alignment between the RTL design team and physical design team. It will provide technical oversight to the physical design team on the physical implementation of the controller and technical guidance to the RTL design team on the creation of designs to meet every more demanding timing-closure challenges.
 
The candidate(s) will be strong in RTL synthesis, constraint generation/validation and timing analysis. They will be capable of generating sub-systems consisting of controller, PHY and SRAM. They will be capable of defining floorplans and pushing the design through front-end placement flows. The successful candidate will be very familiar with physical design.

The successful candidate will be responsible for the handoff from RTL design to physical design and will be responsible for writing customer implementation guides. The candidate will work in a project and team-oriented environment with teams spread across multiple sites, worldwide.
 
Key Qualifications
•    Must have BSEE in EE with 8+ years of relevant experience or MSEE with 6+ years in design and implementation of IP cores and/or SOC
•    Must have experience in Synthesis flows and validating timing constrains
•    Must have experience in design/physical implementation of high frequency interfaces
•    Experience with scripting languages (eg. BASH/TCSH/PERL/PYTHON/TCL)
•    Experience with Verilog, VHDL and/or SystemVerilog
•    Experience with Perforce or similar revision control environment
•    Demonstrate understanding of PHY+CTRL(+SRAM) integration
•    Desired knowledge of one or more of protocols like HBM, DDR, PCIE, USB, MIPI-UFS/Unipro is a plus
•    Desired experience in design and physical implementation in high speed memory interfaces (HBM/DDRx) is a plus

Desired skills  
•    Demonstrate good written and oral communication skills
•    Demonstrate good analysis, debug and problem-solving skills
•    Ability to resolve conflicts and maintain composure under pressure
•    Should be a team player with positive outlook and “can do” attitude