At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars, Artificial Intelligence, The cloud, 5G, The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities, meet unique performance, power, and size requirements of their target applications and get differentiated products to market quickly with reduced risk. 


Job role:
We are looking at Senior Design engineers to work on design and development of RTL based IP Cores implementing complex protocols.  The candidate will be part of the Solutions Group at our Bangalore Design Center, India and will be responsible for implementing RTL based IPs which are used in end-customer applications such as server farms, AI/machine learning, automotive, etc. The candidate will work with our internationally based team of architects/designers/other verification team members across multiple sites worldwide. The position offers learning and growth opportunities. This is a Senior Technical Individual Contributor role and offers challenges to work on technically challenging IP Cores.
Job Responsibilities – Understand Standards / functional specifications for the product and write architecture / microarchitecture specificationsMake architecture decisions on the designImplement RTL design and basic verificationWork with the verification team to define the verification requirementsPerform technical lead role Key Qualifications --
Must have BSEE in EE with 8+ years of relevant experience or MSEE with 7+ years of relevant experience in the following areas:Knowledge of one or more of protocols DDR/PCIE/AMBA (AMBA2, AXI, CHI)/ SD/eMMC/ Ethernet/ USB/ MIPIHands on experience with creating micro-architecture/ detailed design from Functional Specifications  Hands on experience with Verilog/ System Verilog coding and Simulation toolsSynthesis flow and static timing flows, Lint, CDC, Formal checkingPrior experience with SVA and formal verification tools is an added advantageKnowledge of C/C++, TCL, Perl, Python is an added advantage Ability to work independently, precisely and to drive innovationAbility to extract detailed product requirements from high-level specificationGood communication skills.Experience of working with Functional safety, ISO26262 , FMEDA is an added advantage