ASIC Digital Design, Staff Engineer
Sypnosis
Senior Design/Verification - Subsystems Lead:
Greetings from Synopsys ! Synopsys Digital IP Subsystem team grew by leaps and bounds over these years, and we are looking for more talented engineers like you to grow with us !
The cutting edge technological work we do, while we expand our minds to shrink the miniature world of integrated circuits, would pose worthy challenge to fulfill your ambitions in this SysMoore era.
The open positions are in Bangalore/Hyderabad, India. Please follow this post for more information.
Design Lead:As a RTL Design lead, first time bug free RTL from requirement or specification gives you a dopamine rush. Finding an alien life is a complex challenge, however, millions of bug free lines of RTL gives much more satisfaction.We are looking for an expert like you, having done multiple tape-outs, driven the design effort for complex IP/Subsystem/SoC blocks. Verification Lead:As a Verification lead, it is always a fun to catch bugs and ensuring that the design intent is met. Imagine your chip on a space telescope and sending beautiful images of galaxy – verification is the key to avoid white spots mixing with stars.We are looking for an expert like you, having lead multiple tape-outs, closed the verification of complex IP/Subsystem/SoC blocks.
Job role and Skill set – Design role:Senior RTL Subsystems Designer Lead role. With 8+ years of experience.Must be able to drive the Subsystem life cycle from requirement to final release(s) phase(s), crafting the functional specification, defining the micro-architecture, coding the RTL with best practices, driving RTL quality checks and working with Verification and implementation teams, and, all the way to release(s).Proficiency with standard protocols like PCIe, DDR, UFS, USB, AMBA etc.,Hands-on experience with low power design. Understanding of DFT requirements and architecture.Working with cross-functional teams and driving the projects to completion.
Job role and Skill set - Verification role:Senior Verification lead role. With 8+ years of experience.Must be able to drive the complete Verification cycle : crafting the test plan, architecting the verification environment, developing the test infrastructure and executing the plan, driving to closure with coverage.Proficiency with Functional Verification of standard protocols like PCIe, DDR, UFS, USB, AMBA etc.,Power aware Verification with UPF. Gate Level Verification hands-on experience is a value add.Working with cross-functional teams and driving the projects to completion.
Greetings from Synopsys ! Synopsys Digital IP Subsystem team grew by leaps and bounds over these years, and we are looking for more talented engineers like you to grow with us !
The cutting edge technological work we do, while we expand our minds to shrink the miniature world of integrated circuits, would pose worthy challenge to fulfill your ambitions in this SysMoore era.
The open positions are in Bangalore/Hyderabad, India. Please follow this post for more information.
Design Lead:As a RTL Design lead, first time bug free RTL from requirement or specification gives you a dopamine rush. Finding an alien life is a complex challenge, however, millions of bug free lines of RTL gives much more satisfaction.We are looking for an expert like you, having done multiple tape-outs, driven the design effort for complex IP/Subsystem/SoC blocks. Verification Lead:As a Verification lead, it is always a fun to catch bugs and ensuring that the design intent is met. Imagine your chip on a space telescope and sending beautiful images of galaxy – verification is the key to avoid white spots mixing with stars.We are looking for an expert like you, having lead multiple tape-outs, closed the verification of complex IP/Subsystem/SoC blocks.
Job role and Skill set – Design role:Senior RTL Subsystems Designer Lead role. With 8+ years of experience.Must be able to drive the Subsystem life cycle from requirement to final release(s) phase(s), crafting the functional specification, defining the micro-architecture, coding the RTL with best practices, driving RTL quality checks and working with Verification and implementation teams, and, all the way to release(s).Proficiency with standard protocols like PCIe, DDR, UFS, USB, AMBA etc.,Hands-on experience with low power design. Understanding of DFT requirements and architecture.Working with cross-functional teams and driving the projects to completion.
Job role and Skill set - Verification role:Senior Verification lead role. With 8+ years of experience.Must be able to drive the complete Verification cycle : crafting the test plan, architecting the verification environment, developing the test infrastructure and executing the plan, driving to closure with coverage.Proficiency with Functional Verification of standard protocols like PCIe, DDR, UFS, USB, AMBA etc.,Power aware Verification with UPF. Gate Level Verification hands-on experience is a value add.Working with cross-functional teams and driving the projects to completion.
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