ASIC Digital Design, Staff Engineer
Synopsys (formerly Synfora)
Seeking a highly motivated and innovative design engineer with background in high-speed protocols. Working as part of an experienced digital design and verification team. The position offers an excellent opportunity to work with experts on several fields. The candidate will be involved at specify, design and implement phases of state-of-the-art products.
Key responsibilities:Study standard specifications published by JEDECDefine micro architecture at block level based on IP architectureWork on RTL design based on predefined coding style, SVA is includedClean RTL check violations in lint, CDC, DFT and synthesisRun block level test to speed up IP verificationWork with verification to debug and fix RTL issuesCheck synthesis timing and improve RTL design if requiredRequired Skills:Around 5 years of relevant IP design experienceDesire to learn and explore new technologiesDemonstrates good investigation and problem-solving skillsBe familiar with IP design flow and good at RTL designSolid RTL debug capabilityKnowledge in HBM/DDR and interface technologies such as UCie, PCIe, USB is a plusKnowledge in FrontEnd and/or BackEnd synthesis is a plusAbout us
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security.
If you share our passion for innovation, we want to meet you. Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
Key responsibilities:Study standard specifications published by JEDECDefine micro architecture at block level based on IP architectureWork on RTL design based on predefined coding style, SVA is includedClean RTL check violations in lint, CDC, DFT and synthesisRun block level test to speed up IP verificationWork with verification to debug and fix RTL issuesCheck synthesis timing and improve RTL design if requiredRequired Skills:Around 5 years of relevant IP design experienceDesire to learn and explore new technologiesDemonstrates good investigation and problem-solving skillsBe familiar with IP design flow and good at RTL designSolid RTL debug capabilityKnowledge in HBM/DDR and interface technologies such as UCie, PCIe, USB is a plusKnowledge in FrontEnd and/or BackEnd synthesis is a plusAbout us
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security.
If you share our passion for innovation, we want to meet you. Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
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