Position Description:The Candidate will be working on the new processes for physical implementation flows & cutting-edge technology nodes along with other functional teams to optimize and participate in Next Gen PCI/CXL/IDE Controller IP development and define the signoff criteria with strong focus on Timing Closure.The candidate will Work on maturing the physical implementation guide used for the customers & internal hardening teams.The candidate will have the opportunity to work on many varieties of challenging Design configurations and top-class customers. The responsibility includes participating in the next generation physical design methodology and flow development. Perform physical design implementation, including Synthesis, floor-planning, PG Grid design, PnR, CTS, STA, power/signal integrity signoff. The job requirement includes the evaluation of PPA targets (Area/Speed/Power) and co-work with design team to improve the design & constraints.        Position Requirements:         Experienced with ASIC design flow, hierarchical physical design strategies, and methodologies and understand deep sub-micron technology issues. Solid knowledge on FC Design planning methodologies, floor-planning, PG Grid creation using Synopsys Tools. Innovative, self-motivated, able to work independently or as a team player, excellent verbal, and written communication .Strong physical implementation flow debugging skills.Strong scripting skills.Desire understanding of RTL/Timing signoff criteria.