Acacia, part of Cisco, provides innovative silicon-based high-speed optical interconnect products to accelerate network scalability through advancements in performance, capacity, and cost. Our DSP ASICs, silicon photonic PICs, and coherent modules empower cloud and service providers to meet the fast-growing demand for data. We have assembled a team of cross-functional experts capable of solving the challenges of next-generation optical interconnects, resulting in industry-leading, award-winning products. Come join us at Cisco, named the #1 world’s best workplaces, and do purposeful work that makes a global impact and gives back to a company culture that empowers an inclusive future for all.
Your ImpactThe ASIC Design Verification Technical Lead Engineer will be working on next-generation 100G-1.6T coherent optical communications products. This role is for a senior contributor & technical leader focused on verifying highly complex ASICs that are used in these next-generation systems. The role requires someone to demonstrate their experience applying sophisticated verification techniques to ASIC projects: ensuring design quality, leading sophisticated technical projects, developing process improvements for the team, and mentoring teammates on techniques, technology & methods for verification. This role also requires significant communication skills (both written and verbal) to contribute to the ASIC projects, and working with other technical leaders in the engineering community.
This Technical Lead Engineer will need to operate independently with minimal direction in a fast-paced, dynamic, and highly technical environment, creating unique verification solutions and providing technical leadership to others on the team. A successful candidate will be highly self-motivated, collaborative, and passionate about delivering the most advanced high-speed optical products in the world. Knowledge of object-oriented verification methodologies is required.
Lead and develop detailed and comprehensive test plansLead and Develop verification test benchesApply innovative verification techniques to complex designsSupervise the timely execution of test plans by the rest of the teamLead and assist with chip-level design tradeoffs by working with design engineersParticipate in the review of design verification coding and coverage metricsProvide technical leadership & mentoringParticipate and assist in FPGA emulation effortsWork collaboratively with the team to develop & incorporate the latest test technologies & processesMinimum Qualifications:Bachelor's or Master’s degree majoring in Computer Science, Computer Engineering, or Electronic or Electrical Engineering, with 10 or more years of experienceExtensive experience with the latest ASIC verification methodologies, tools, and scripting/programming languagesExtensive experience with SystemVerilog/UVM, SystemCExperience with C and/or C++Preferred Qualifications:Consistent track record of innovation that leads to quantifiable improvementsSelf-motivation and the ability to implement effectively without supervisionKnowledge of DSP algorithms and modulation techniques such as QAM is a plusLab silicon validation experience is a plusKnowledge of Formal Verification methodologies and tools such as Jasper or VCFormal is a plus#WeAreCisco#WeAreCisco where every individual brings their unique skills and perspectives together to pursue our purpose of powering an inclusive future for all.
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