**Summary:** Meta is seeking an ASIC Engineer to join our Infrastructure organization. Our servers and data centers are the foundation upon which our rapidly scaling infrastructure efficiently operates and upon which our innovative services are delivered. By holding this role, you will be an integral member of an ASIC team to build accelerators for some of our top workloads enabling our data centers to scale efficiently. You will have an opportunity to participate in design implementation of advanced IPs using state-of-the-art tools. Come work and learn alongside our ASIC engineers to build “Green” data center accelerators. **Required Skills:** ASIC Engineer, Physical Design Responsibilities: 1. Develop and own physical design implementation of multi-hierarchy low-power and high-performance designs, including physical-aware logic synthesis, floorplan, place and route, clock tree synthesis, static timing analysis, IR drop, EM, and physical verification in advanced technology nodes. 2. Resolve design and flow issues related to the physical design, identify potential solutions, and drive execution. 3. Deliver physical design of an end-to-end IP or integration of ASIC/SoC design and point out lower power and higher performance trade-offs. 4. Work with the RTL design team to understand partition architecture and drive physical aspects early in the design cycle. 5. Use EDA tool-based programming and scripting techniques to automate and improve throughput and quality. 6. Interact with tool vendors to drive tool fixes and flow improvements. Perform tool evaluations of new vendor tools and functions. 7. Drive logic/physical synthesis and generate optimized Gate level Netlist for Physical Design. **Minimum Qualifications:** Minimum Qualifications: 8. Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta. 9. Programming/scripting skills: TCL, Python, or Shell 10. Knowledge of geometry/process/device technology implications on physical design 11. Knowledge of Computer Architecture, Digital Design or VLSI Design 12. Knowledge of RTL2GDSII flow 13. Knowledge of CMOS Technology, Logic Gates, Flip Flops or similar 14. Must obtain work authorization in the country of employment at the time of hire and maintain ongoing work authorization during employment **Preferred Qualifications:** Preferred Qualifications: 15. Knowledge of Verilog, VHDL or similar hardware description language 16. Experience with Logic Synthesis 17. Knowledge of static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions 18. Understanding of SRAM Memories **Public Compensation:** $114,000/year to $133,000/year + bonus + equity + benefits **Industry:** Internet **Equal Opportunity:** Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment. Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@fb.com.