**Summary:** Meta is hiring ASIC Power Engineers within our Infrastructure organization to work on power/performance optimizations from SOC Architecture to System level. We are looking for individuals with experience in power architecture definition and power management for large complex disaggregated ASICs to build efficient System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer, Power (University Grad) Responsibilities: 1. Work with Architecture and Design teams to assess power/performance tradeoffs at design/arch/process-tech levels and drive for solutions for Meta workloads. 2. Define the power specification at system and module level for Idle, TDP, typical use cases. 3. Develop power modeling infrastructure in Python/C++. 4. Work with or develop architectural simulators in order to model performance and power. 5. Build power estimation flows at various levels of abstraction: C-model, RTL, Gate, Layout. 6. Power characterization on silicon: idle, TDP, use case power & debug power issues on silicon. 7. Partner with vendors to drive low-power requirements for SoC interfaces such as LPDDR, PCIe, etc. 8. Partner with EDA tool vendors to select and deploy the appropriate power estimation tools. **Minimum Qualifications:** Minimum Qualifications: 9. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. 10. Experience with power arch specification, modeling, and design with C++/Python or an equivalent high level language. 11. Experience with EDA tools and scripting languages (Python, TCL) used to build tools and flows for complex environments. **Preferred Qualifications:** Preferred Qualifications: 12. Understanding of ASIC design process and knowledge of leakage and dynamic power, and impact of environment and manufacturing process on power. 13. Experience with communicating across functional internal teams and with vendors Knowledge of front-end and back-end ASIC tools. 14. Experience with RTL design using System Verilog or other HDL. **Industry:** Internet