Who you are:
BS/MS in Electrical Engineering or Computer Science.10+ years of hands-on experience in ASIC design. Excellent Verilog/System Verilog programming skills.Knowledge of Silicon Lifetime Managements IP, their usage,  verification specs.Experience with simulators/synthesis/static timing constraints and tools.Good understanding of verification methodologies and flow.Strong interactive and waveform debug skills.Excellent English verbal and written communication skills.Self-motivated, able to work independently or as a team player.Experience in block level synthesis, place and route, timing closure is highly desirable.Scripting experience (Python, Perl, TCL, shell programming) highly desirable.