ASIC STA Engineer
Cisco Systems
Who We AreThe Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry.
What You'll DoThis role expects you to be responsible for closing timing at block, sub-chip, and full-chip levels, performing quality checks such as setup, hold, transition, and noise, while managing ECO tasks. Your role may include extraction and STA flow development, convergence strategies, and correlation between PNR, Spice, and STA, along with advising the Physical Design team on best practices. Additionally, you’ll develop methodologies, guidelines, and checklists to streamline STA work, resolve design and flow issues, and drive execution to ensure progress and accuracy. Who you’ll work with You will collaborate with ASIC Front-end and Back-end teams to understand chip architecture and guide them in refining design and timing constraints for seamless physical design closure. As part of this team, you’ll be working closely with the timing lead on backend timing signoff, including CDC checks, static timing verification, and silicon debugging.
Who You Are Experience in generating timing constraints and performing quality checks such as setup, hold, transition, and noise. Timing closure with various timing ECO including transition, setup, hold, noise, crosstalk, and power recovery.Familiarity with various on-chip variation including AOCV, POCV and voltage, temperature, aging-based timing derates Proficient in synthesis constraints and using industry standard synthesis tools. Good written and verbal communication skills. Collaborative and team-focused with the commitment to learn and grow. Minimum Qualifications Bachelor’s degree in electrical or computer engineering (or other equivalent field) with 5+ years of related work experience. Prior experience using Synthesis Tools: Synopsys DC/DCG/FC. Prior experience in Static Timing Analysis & ECO: Synopsys Primetime/Cadence Tempus. Prior experience with scripting such as TCL, Perl, or Python.Preferred QualificationsMaster’s degree in electrical or computer engineering (or other equivalent field) with 2+ years of related work experience. Experience using: Synopsys PTPX/Tweaker/PrimeClosure Experience using Formal Verification: Synopsys Formality and Cadence LEC. Experience using Parasitic Extraction: Synopsys Star-RCXT, Cadence Quantus.
Why Cisco?
#WeAreCisco. We are all unique, but collectively we bring our talents to work as a team, to develop innovative technology and power a more inclusive, digital future for everyone. How do we do it? Well, for starters – with people like you!
Nearly every internet connection around the world touches Cisco. We’re the Internet’s optimists. Our technology makes sure the data travelling at light speed across connections does so securely, yet it’s not what we make but what we make happen which marks us out. We’re helping those who work in the health service to connect with patients and each other; schools, colleges and universities to teach in even the most challenging of times. We’re helping businesses of all shapes and size to connect with their employees and customers in new ways, providing people with access to the digital skills they need and connecting the most remote parts of the world – whether through 5G, or otherwise.
We tackle whatever challenges come our way. We have each other’s backs, we recognize our accomplishments, and we grow together. We celebrate and support one another – from big and small things in life to big career moments. And giving back is in our DNA (we get 10 days off each year to do just that).
We know that powering an inclusive future starts with us. Because without diversity and a dedication to equality, there is no moving forward. Our 30 Inclusive Communities, that bring people together around commonalities or passions, are leading the way. Together we’re committed to learning, listening, caring for our communities, whilst supporting the most vulnerable with a collective effort to make this world a better place either with technology, or through our actions.
So, you have colorful hair? Don’t care. Tattoos? Show off your ink. Like polka dots? That’s cool. Pop culture geek? Many of us are. Passion for technology and world changing? Be you, with us! #WeAreCisco
What You'll DoThis role expects you to be responsible for closing timing at block, sub-chip, and full-chip levels, performing quality checks such as setup, hold, transition, and noise, while managing ECO tasks. Your role may include extraction and STA flow development, convergence strategies, and correlation between PNR, Spice, and STA, along with advising the Physical Design team on best practices. Additionally, you’ll develop methodologies, guidelines, and checklists to streamline STA work, resolve design and flow issues, and drive execution to ensure progress and accuracy. Who you’ll work with You will collaborate with ASIC Front-end and Back-end teams to understand chip architecture and guide them in refining design and timing constraints for seamless physical design closure. As part of this team, you’ll be working closely with the timing lead on backend timing signoff, including CDC checks, static timing verification, and silicon debugging.
Who You Are Experience in generating timing constraints and performing quality checks such as setup, hold, transition, and noise. Timing closure with various timing ECO including transition, setup, hold, noise, crosstalk, and power recovery.Familiarity with various on-chip variation including AOCV, POCV and voltage, temperature, aging-based timing derates Proficient in synthesis constraints and using industry standard synthesis tools. Good written and verbal communication skills. Collaborative and team-focused with the commitment to learn and grow. Minimum Qualifications Bachelor’s degree in electrical or computer engineering (or other equivalent field) with 5+ years of related work experience. Prior experience using Synthesis Tools: Synopsys DC/DCG/FC. Prior experience in Static Timing Analysis & ECO: Synopsys Primetime/Cadence Tempus. Prior experience with scripting such as TCL, Perl, or Python.Preferred QualificationsMaster’s degree in electrical or computer engineering (or other equivalent field) with 2+ years of related work experience. Experience using: Synopsys PTPX/Tweaker/PrimeClosure Experience using Formal Verification: Synopsys Formality and Cadence LEC. Experience using Parasitic Extraction: Synopsys Star-RCXT, Cadence Quantus.
Why Cisco?
#WeAreCisco. We are all unique, but collectively we bring our talents to work as a team, to develop innovative technology and power a more inclusive, digital future for everyone. How do we do it? Well, for starters – with people like you!
Nearly every internet connection around the world touches Cisco. We’re the Internet’s optimists. Our technology makes sure the data travelling at light speed across connections does so securely, yet it’s not what we make but what we make happen which marks us out. We’re helping those who work in the health service to connect with patients and each other; schools, colleges and universities to teach in even the most challenging of times. We’re helping businesses of all shapes and size to connect with their employees and customers in new ways, providing people with access to the digital skills they need and connecting the most remote parts of the world – whether through 5G, or otherwise.
We tackle whatever challenges come our way. We have each other’s backs, we recognize our accomplishments, and we grow together. We celebrate and support one another – from big and small things in life to big career moments. And giving back is in our DNA (we get 10 days off each year to do just that).
We know that powering an inclusive future starts with us. Because without diversity and a dedication to equality, there is no moving forward. Our 30 Inclusive Communities, that bring people together around commonalities or passions, are leading the way. Together we’re committed to learning, listening, caring for our communities, whilst supporting the most vulnerable with a collective effort to make this world a better place either with technology, or through our actions.
So, you have colorful hair? Don’t care. Tattoos? Show off your ink. Like polka dots? That’s cool. Pop culture geek? Many of us are. Passion for technology and world changing? Be you, with us! #WeAreCisco
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