Role Proficiency:

Execute any internal project or small tasks of customer project in any field of VLSI Frontend Backend or Analog design under minimal supervison from the Lead

Outcomes:

     As an Individual contributor work on any one task of RTL Design/Module in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff etc.      Analyse and complete the assigned task in the defined domain(s) successfully on-time with minimal support from senior engineers Ensure quality delivery as approved by the senior engineer or project lead

Measures of Outcomes:

     Quality –verified using relevant metrics by Lead/Manager      Timely delivery - verified using relevant metrics by Lead/Manager      Reduction in cycle time and cost using innovative approaches      Number of trainings attended

Outputs Expected:

Quality of the deliverables:

Clean delivery of the module in-terms of ease in integration at the top level Ensure functional spec / design guidelines are met 100% of the time without deviation or limitation Documentation of the tasks and work performed

Timely delivery:

Meet project timelines as given by the team lead/program manager Help with intermediate tasks delivery by other team members to ensure progress

Teamwork:

Teamwork participation; supporting team members in the time of need Able to perform additional tasks in case of any team member(s) is not available

Innovation & Creativity:

Pro-actively plan approach towards repeated work by automating tasks to save design cycle time Participation in technical discussion
training
forum

Skill Examples:

     Languages and Programming skills:a.     System Verilog Verilog VHDL UVM C C++ Assembly Perl TCL/TK Makefile Spice (any one)      EDA Tools: a.     Cadence Synopsys Mentor tool sets (one or more)b.     Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS PT/Tempus Calibre etc. (any one)      Technical Knowledge: (any one)a.     Understands IP Spec Architecture Design Micro Architecture Functional Spec Test Plan Verificationb.     Knows Bus Protocol AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Microprocessor architecturec.      Good knowledge of Physical Design / Circuit Design / Analog Layout d.     Good understanding of Synthesis DFT Floorplan Clocks P&R STA Extraction Physical Verificatione.     Knowledge in Soft / Hard / Mixed Signal IP Design Processor Hardening FPGA Design      Technology: CMOS FinFet FDSOI - 28nm / 22nm / 16ff / 10nm and below      Required technical skills and prior design knowledge to execute assigned tasks      Ability to learn new skills in case required technical skills are not present to a level needed to execute the project      Able to deliver tasks with quality and 100% on-time per quality guidelines and GANTT      Strong communication skills Good analytical reasoning and problem-solving skills with attention to detail

Knowledge Examples:

     Previous project experience in any of the design by executing any one of the following RTL Design / Verification / DFT / Physical Design / STA / PV / Circuit Design / Analog Layout etc.      Good Understanding of the design flow and methodologies used in designing      Understand the assigned tasks and have sufficient knowledge to execute the project tasks assigned by the client / manager per skill set

Additional Comments:

Desired Skills and Experience: • Engineers is expected to be very good in Basic Fundamentals of C-MOS technology • Expected to have a very good understanding of the PD Flow fand able to handle RTL/Netlist to GDSII independently at block level and should have done multiple tape outs (Low power implementation is preferred) • Should have hands-on experience of working on Lower technology nodes like 5nm, 7nm, 10nm, 14nm, 16nm, 28nm etc. • Hands-on experience in floor planning, placement optimizations, CTS and routing. Hands-on experience in block/top level signoff STA, physical verification (DRC/LVS/ERC/antenna) checks and other reliability checks(IR/EM/Xtalk) • Should have expertise on industry standard EDA tools from Synopsys , Cadence and Mentor • ( ICC2, Fusion-Compiler, Design Compiler, Primetime, PTSI, IC Validator, Innovus, Genus, Tempus, Encounter, Nanoroute, Calibre, StarRC and Redhawk, voltage storm • Exposure in DMSA flow for ECO generation and implementation. • Good knowledge of VLSI process and scripting in TCL, perl .