Associate III - VLSI
UST Global Inc
IO Layout
Exp-4 to 8
Hands on experience in IO block-level/full-module layout design
Experience in developing IO's from scratch including floor-planning,Power bus design, ESD & PAD cell will be preferred.
Hands on experience with Calibre & PVS verification platforms.
Good knowledge on IC Fabrication, layout-design fundamentals & reliability issues.
Good Knowledge on IO basics & different IOs.
Experience in FinFET technologies will be highly preferred.
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