Additional Comments:

B. Tech. / M. Tech. with 4+ years of experience as a DFT Engineer In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis. Analyze design and propose best compression technique. Debug and resolve the DRC issues. Work with front end team to provide the solutions and make sure DFT DRCs are fixed. Generating high quality manufacturing ATPG test patterns for (SAF) stuck-at, transition fault (TDF), Path Delay fault (PDF) models and through the use of on-chip test compression techniques. Working experience in Synopsis TetraMax/DFTMax and Cadence Encounter Test is required. In depth knowledge and hands on experience in MBIST insertion and Memory test validation. Expertise in Mentor tools is plus.