Number of Position(s): 1

Duration: 10 Weeks 

Date: June 8 – Aug 14, 2026

Location: On-site in Murray Hill, New Jersey.
 

EDUCATIONAL RECOMMENDATIONS

Currently a candidate for a PhD degree in Computer Science, Electrical Engineering, Computer Engineering, or Engineering in VLSI and telecommunication or related field with an accredited school in the USA. 

*Highly qualified Master's degree students will be considered
 

You have at least TWO of the following:

AI/ML programming frameworks: TensorFlow, PyTorch, Keras, etc.Background in compiler design and advanced computer architectureProgramming for parallel systems and/or CUDA for GPU programming.Software-defined networks and real-time signal processing using DSPsAdvanced RTL development skills and fluent in HDL (Verilog, SystemVerilog, and VHDL) and/or HLS (High-level Synthesis)Experience in ASIC physical design: circuit layout using Cadence (Innovus, Spectre, Virtuoso) and Synopsys (VCS, ICC)Knowledge in gate or RTL-level design optimization, timing closure analysis, and/or mixed-signal circuit design

As a part of our team, you will: 

Work with seasoned Bell Labs researchers on the design and development of ASIC and/or proof-of-concept system platformParticipate in a research project, work with mentor(s) to define, develop and conduct a research projectAttend research talks in various technology areas
 

Platform and ASIC (PAR) research project will be in any of the following areas:

Acceleration of Artificial Intelligence/Machine Learning (AI/ML) modelsDigital signal processing and accelerator for 5G/6G communication systemsSoftware-defined cloud-based radio access network (RAN)New materials/devices, e.g. Memristor, for high-performance computing or signal processing Application of AI/ML in SoC and system platform design