Do you want to contribute to the backbone of some of the world’s most popular SoCs? Arteris enables engineering and design teams at the world’s most transformative brands to connect and integrate today’s system-on-chips (SoCs) that fuel modern innovation. If you’ve held a smartphone, driven an electronic car, or powered up a smart TV, you’ve come in contact with what we do at Arteris. Here, the future is quite literally in your hands—and when it isn’t, chances are it is flying overhead in a drone, a satellite, or in the cloud at a datacenter! As a Cache Coherency Architect at Arteris you will be an important contributor, defining and optimizing cache coherency solutions within Arteris' advanced IP portfolio. Your primary focus will be on developing cutting-edge cache coherent interconnect IP and ensuring seamless integration with other NoC interconnects, and system IP to support efficient and coherent communication between multiple processor and accelerator cores and functional units. You will collaborate closely with hardware designers, verification engineers, software developers, and other stakeholders to create high-performance, power-efficient, and reliable NoC IP solutions. Key Responsibilities: Cache Coherency Architecture:       Evaluate existing, industry standard, cache coherency protocols, maintain and improve our proprietary coherency protocol which is used within Arteris' highly configurable NoC IP        Develop comprehensive and scalable cache coherency architectures that align with the overall System-on-a-Chip (SoC) design        Analyze our customer's requirements for cache coherent system architectures, also considering partitioning large designs into chiplets using die-to-die and chip-to-chip architectures based on industry wide standards like CXL, UCIe and PCIe        Set performance goals (PPA) for the configurable IP NoC Integration:       Collaborate with SoC design teams to ensure seamless integration of cache coherency into the SoC architecture        Help to optimize Cache Coherency Architecture and uArchitecture within the NoC to minimize latency and improve BW Performance and Power Optimization:       Analyze performance bottlenecks and power consumption aspects, proposing and implementing innovative solutions to enhance overall efficiency        Collaborate with hardware and software teams to verify and optimize cache coherency mechanisms Protocol Verification:       Support the verification team to develop verification strategies to ensure the correctness and robustness of the cache coherency protocols and the implementation within our NoC IP        Support the emulation teams testing and debugging to validate cache coherency behaviors under various scenarios for functional correctness and performance Cross-Functional Collaboration:       Interact with the marketing and sales teams to collect customer input and understand market and product requirements        Collaborate with hardware design, software development, and system architecture teams to understand their needs and issues        Provide technical expertise and support to the FAE team to assist in the integration of our products within our customer's designs Industry Research and Innovation:       Stay up-to-date with the latest advancements and research in cache coherency and NoC technologies.        Evaluate emerging methodologies, standards, and industry trends, proposing their integration to enhance our NoC IP offerings. Documentation and Communication:       Prepare detailed technical documentation, including architecture specifications and design guidelines/white papers.        Effectively communicate complex technical concepts to both technical and non-technical stakeholders. Qualifications:        Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.        Proven experience as a Cache Coherency Architect, Design Engineer, or similar role with a focus on NoC IP development.        In-depth knowledge of SoC and NoC architecture, cache coherency protocols, and memory hierarchy.        Strong understanding of cache hierarchies and their interaction with NoC interconnects.        Experience in cache coherency verification and validation techniques.        Familiarity with hardware description languages (HDLs) and SoC design tools.        Strong analytical and problem-solving skills with a strategic mindset.        Excellent communication and collaboration abilities to work effectively with diverse teams and stakeholders.        Familiarity with hardware description languages (HDLs) and design tools used in NoC IP development or prior experience in designing coherent systems is highly advantageous. Joining our team as a Cache Coherency Architect for our NoC IP development offers a unique opportunity to contribute to the creation of state-of-the-art semiconductor solutions. This is a highly visible role within the entire organization. If you are passionate about cache coherency, NoC IP design, and eager to drive innovation in the semiconductor industry, we encourage you to apply and be part of our dynamic and forward-thinking team. Estimated Annual Base Salary:  $175,000 to $235,000 annually ​About Arteris: Arteris is a leading provider of system IP for the acceleration of system-on-chip (SoC) development across today’s electronic systems. Arteris network-on-chip (NoC) interconnect IP and SoC integration automation technology enable higher product performance with lower power consumption and faster time to market, delivering better SoC economics so its customers can focus on dreaming up what comes next.    With over 250 employees with headquarters in Silicon Valley and offices around the globe, we are a catalyst for SoC innovation so companies ranging from startups to the biggest technology market leaders can effectively create new products with proven connectivity flexibility and ease.  Learn more at arteris.com.