Company:Qualcomm India Private Limited

Job Area:Engineering Group, Engineering Group > Hardware Engineering

General Summary:

As a Physical Design Engineer, you will work with microarchitecture, RTL design and CAD teams to implement the designs meeting aggressive power, area and performance goals using industry standard tools/flows.

Roles and Responsibilities

Perform block level implementation using place and route techniques to meet area/timing and power requirementsCreate floorplan with pin placement, partitions and power gridGenerate block level static timing constraintsPerform Synthesis, Place & Route on the designs using industry standard tools and deliver GDSValidate the designs for functional and electrical robustnessGenerate and implement ECOs to fix noise, timing and EM/IR violationsInvolve in defining correct by construction physical design methodologies.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Preferred qualifications

MS degree in Electrical Engineering; 5 to 15 years of practical experienceExperience in developing and implementing power grid and clock specificationsExperience in all aspects of timing closure for multi-clock domain designsExperience in deep submicron process technology nodes is strongly preferredKnowledge of library cells and optimizationsSolid understanding industry standard tools for synthesis, place & route and tapeout flowsSolid understanding of physical design verification methods to debug LVS/DRC. Experience with Synthesis, place and route and signoff  timing/power analysisKnowledge of all aspects of physical construction, integration, physical and electrical verification Knowledge of basic SoC architecture and HDL languages like Verilog.

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