Lead the unit level pre-silicon functional & performance verification of the front end of the pipeline for our next -generation IBM POWER processor core systems offering.Architect and enhance the existing verification environment for Instruction fetch, Branch Prediction and Instruction Decode units of the high performance processor CPU.Develop verification test plan for both functional and performance verification including the estimation for coverage closure.Support higher level core/system simulation environment.Participate in post silicon lab bring-up and validation of the Hardware.Lead, guide, mentor a team of engineers and represent them at global forums.Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement.Effectively Communicate progress, potential challenges encountered and milestones achieved to stake holders and team members.