The Cadence Silicon Solution Group (SSG) develops industry leading IPs that enable our customers in a variety of markets - from the endpoint to the edge to the cloud and AI for SoC and chiplets. At Cadence we’re helping set the standard on IP products that get integrated in SoCs and chiplets powering the world’s Data Centers, Automobiles, Cloud, wired/Wireless, and AI enabled systems. Cadence SSG IP business is growing fast. We’re expanding our San Jose team and looking for smart, energetic, collaborative and creative people to join this exciting growth opportunity and help us lead the industry with Cadence IP products for silicon solutions. Do you want to make a difference and be challenged?
Design Engineering Architect in physical design, SSG.
• This technical and project leadership role is responsible for working with IP design teams and silicon solution architects to develop new physical aware IP architectures, collaborating with leading foundries such as TSMC, Samsung, Intel to achieve best Performance/Power/Area (PPA) for Cadence IPs, and guiding Cadence worldwide physical design teams to follow the best design practices and methodologies.
• The position requires 15+ years of experience in design tools, foundry technologies and proven leadership in collaborating and coordinating cross functional teams and external companies to develop industry-leading IPs for advanced technology nodes at world leading semiconducdor foundries.
• Cross functional project management experience with strong communication and inter-personal skills are required.
• Thorough understanding and experience with the full physical design flows including RTL Synthesis, floorplan, P&R, high performance clock-tree synthesis, static Timing analysis and closure, DFT, Low power design techniques, Physical verification.
• Deep knowledge and experience with Cadence tools/flows (Genus, Innovus, Voltus, Tempus, Modus, Conformal-LP, Pegasus).
• Good knowledge with high performance interface PHYs and controllers is highly desirable.