Job Description

Performs functional verification of IP logic to ensure design will meet specification requirements.

Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications.

Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs.

Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams.

Maintains and improves existing functional verification infrastructure and methodology. Participates in the definition of verification infrastructure and related TFMs needed for functional design verification.

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Minimum Qualifications:

Bachelors Degree in Computer Science, Computer Engineering or Electrical Engineering or another STEM related degree with 8+ years' experience OR

Masters Degree in Computer Science, Computer Engineering or Electrical Engineering or another STEM related degree with 6+ years' experience

5+ years' work experience:

working on IP or SoC development, verification, or integration using System Verilog/OVM/UVM

writing validation plans implement those validation plans using System Verilog

Preferred Qualifications:

3+ years of experience with DFI/DDR/LPDDR Protocols

3+ years of experience with DDR Phy verification or Memory Controller verification

Inside this Business Group
The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

Other Locations

US, OR, Hillsboro; US, AZ, Phoenix; US, CA, Santa Clara


Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.



Annual Salary Range for jobs which could be performed in the US $161,230.00-$227,620.00
*Salary range dependent on a number of factors including location and experience


Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.