**Introduction** We are seeking energetic, highly motivated individuals willing to go the extra mile with the aim of helping the overall IBM development team. Strong interpersonal skills are needed to coordinate deliverables and requirements from several areas within and outside of the organization. There are many opportunities to gain and utilize a deep understanding of future issues and provide input towards decisions affecting system development, logical and physical design as well as sophisticated methodology directions. **Your role and responsibilities** In this role, you are expected to * Efficient in LVS/DRC Runset development * Hands on experience in working on LVS and DRC runset development and support * Knowledge/Exposure in lower process node * Have excellent debugging skills. * Have strong interpersonal skills needed to coordinate deliverables and requirements from several areas within and outside of the organisation. * Have familiarity with ICV , Calibre Physical Design Verification Tool **Required technical and professional expertise** * 2-5 years of Chip Layout and Runset Coding (ICV / Calibre ) * Chip layout fundamentals (understanding the layers and how they connect and the rules on sizing and spacing and the electrical connectivity logic) * Runset coding in general, ICV pxl in particular * Basic SKILL code (for interfacing with Virtuoso) * Basic TCL for interfacing with Custom Compiler and ICV * Basic Python scripting * VLSI knowledge * Proven problem-solving skills and the ability to work in a team environment are a must * EDA tool development experience **Preferred technical and professional experience** * Cadence,Synopsys,VLSI Knowledge