Company:Qualcomm India Private LimitedJob Area:Engineering Group, Engineering Group > Hardware Engineering
General Summary:
General Summary:
ResponsibilitiesFront-End implementation of SERDES high speed Interface PHY designsRTL development and its validation for linting, clock-domain crossing, conformal low power and DFT rules.Work with functional verification team on test-plan development and debug.Develop timing constraints, deliver synthesized netlist to physical design team, and provide constraints support for PD STA.UPF writing, power aware equivalence checks and low power checks.DFT insertion and ATPG analysis for optimal SAF, TDF coverage.Provide support to SoC integration and chip level pre/post-silicon debug.
Skills & Experience
Minimum Qualifications:
• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
Minimum Qualifications:
• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
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