Job Duties:
A verification engineer should be able to create test plans and testbenches to verify both logic and microcode provided by logic designers.  They should communicate with the logic designer to create and review a test plan document, and then implement a testcase from the document.   Testcases are written in either cycle sim or event sim, depending on the application.  Simulations should be randomized appropriately and executed in large numbers through batch submissions.  Coverage should be collected and analyzed with the logic designer.  Some amount of logic debug ability is expected.

About the Team:
The team in Austin, TX consists of analog circuit designers, logic designers, and verification engineers.  We work with a global team to deliver IBM’s proprietary high speed interfaces for its server processors.  

Skills:
High-speed IO or Analog Mixed Signal Verification experience preferred, Testbench design, Automated testcase design (Fusion/C++), Sim coverage collection and analysis, Batch submission and queue management, Randomization management, General communication skills (written and on the phone)

Tools:
C/C++, SystemVerilog, UVM, Git, VHDL, AMS verification, Linux OS, KornShell & BASH scripting, NCSim, MESA / Fusion, HDWB, AWAN, Mantis, PSL