- Experience in Analog Mixed-signal layout and verification , experience in high-speed SerDes IPs is a plus.
- Advanced understanding of Deep submicron effects and mitigation, Advanced tool usage, Floor-planning , Routing.
- Solid understanding of CMOS and FinFET layouts and process technology in 28nm and below.
- Good understanding of basic ESD and latch-up layout design considerations.
- Excellent written and verbal communication skills in interactions with internal development teams.