Experience Required: 6+ years

Education: Btech/Mtech Electronics/Electrical engineering

Skills/Experience:

- Experience in Analog Mixed-signal DDR/HBM IP layout and verification of high-speed digital layout and solid understanding of high speed signal

- Advanced understanding of Deep submicron effects and mitigation, Advanced tool usage, Advanced floorplanning techniques, understand digital flow, Advanced strategies.

- Solid understanding of CMOS and FinFET layouts and process technology in 28nm and smaller.

- Good understanding of ESD and latchup layout design considerations.

- Familiarity with ASIC physical design flow: LEF generation, Place & Route & understanding of top level verification flow, DRC/LVS, LPE.

- Good understanding of IO frame and pitch requirements, power rail routings, IO abutment rules and requirements, bondpad layout, EM and IR considerations, DFM, etc.

- Scripting skills for layout automation is a plus

- Remote site interaction, layout co-ordination activities, ability to foster accountability and ownership through hands-on technical leadership.

- Excellent written and verbal communication skills in interactions with customers, and internal development teams.

Responsibilities:

- High Speed DDR/HBM Layout design

- Provide subject matter expertise & technical leadership in High Speed design such as DDR/HBM.

- Work with DDR PHY team, package engineers and system engineers to meet design specs.

- Perform scheduling duties, Remote site interaction etc.

- Work with local team to support critical layout and floorplanning requirements

- Coordination duties with other layout teams both in Bangalore and globally, to detail out layout activities and obtain layout deliverables. This includes reviewing and quality checking from remote Layout teams.

- Strict flow adherence and policing of internal policies to secure schedules.