Qualification:
Experience Required: 2 to 6 years.
Education: Btech/Mtech Electronics/Electrical engineering

Skills/Experience:
- Experience in Analog Mixed-signal layout and verification of high-speed digital and/or DDR/HBM IP’s.
- Advanced understanding of Deep submicron effects and mitigation, Advanced tool usage, Advanced floorplanning techniques, understand digital flow, Advanced strategies.
- Solid understanding of CMOS and FinFET layouts and process technology in 28nm and smaller.
- Good understanding of basic ESD and latchup layout design considerations.
- Familiarity with ASIC physical design flow: LEF generation, Place & Route & understanding of top-level verification flow, DRC/LVS, LPE.
- Good understanding of IO frame and pitch requirements, power rail routings, IO abutment rules and requirements, bondpad layout, EM and IR considerations, DFM, etc.
- Knowledge of DDR/HBM PHY and conducting comprehensive reviews of customer implementation is an asset
- Excellent written and verbal communication skills in interactions with customers, and internal development teams.

Responsibilities:
- Conduct comprehensive reviews of customer PHY implementations, including assessing the timeline, deliverables, and adherence to best practices
- Solving customer problems and provide the guidance on PHY implementation, usually requires deep investigation of PHY implementation
- Serve as subject matter expert on implementation best practices, sharing insights and knowledge with internal teams and customers as needed
- Develop and maintain documentation to supports customer throughout the review process
- Contribution to implementation guideline, databook, application note and white papers
- Collaborate with cross functional teams to gather feedback and insights on customer experience during the review process
- Strict flow adherence and policing of internal policies to secure schedules.