At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.To provide key technical support in digital IC design implementation, product demonstration, and sales presentations.To demonstrate strong ability and to be hands-on in RTL-to-GDSII design methodology, including both challenging low power and high-performance designs.Assist in technical evaluation, assessment and delivery of concurrent ASIC/SoC designs.To play a leading role among other team members, while receive little instruction on routine and general assignments.

requirements:

Master with 3+ years working experience or Bachelor with 6+ years’ experience in IC design.Have real design experience including floorplan and partition, place, CTS, route, STA timing closure, Physical verification, RC extraction, Power Network analysis.  Synthesis experience will be a plus. Advance node N5, N3 experience will be a plusAbility to understand and articulate technical issues, (and knowledge of) design products and their applications.Requires working knowledge of one or more programming languages, and effective communication and soft skills.An MS degree and/or working experience in multi-nation IC design house/or familiar with EDI/Innovus product is a plus.good work attitude and good communicationBe familiar with shell/Perl/Tcl etc.We’re doing work that matters. Help us solve what others can’t.