At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Be part of the Cadence DDR PHY IP Front End Design team responsible for - 

Developing firmware for DDR PHY using microcontrollersResponsible for developing firmware in C and similar Embedded programming languages typically involving bare-metal programming and developing low-level APIs on Microcontrollers.Responsible for collaborating with hardware designers and memory subsystem architects to derive algorithms and implement them.Responsible for collaborating with the verification team to deduce firmware-hardware co-verification plan.Support debug of firmware-based simulations in hardware behavioral simulations (RTL simulations with firmware for verification)We’re doing work that matters. Help us solve what others can’t.