PUNE, India
11 days ago
Lead Design Engineer
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.Experience in developing complex test bench in System Verilog using OVM/UVM methodologyExperience in coding functional coverage and system verilog assertions.Experience validation of protocols such as AXI4, AHB, functionality like DMA (Direct Memory Access Controllers), Arbiters.Knowledge of computer architecture, AI accelerators is a big plus.Well versed with System Verilog and popular EDA (Cadence Xcelium preferred) simulation, System Verilog assertions and testbench methodologiesExposure to scripting languages like Perl, Unix shell or similar languagesExcellent written and oral communication skills necessary

Job Role:

He/She will be a part of design verification team supporting the DNA (Deep Neural Accelerator) product line.Work closely with the designers/micro-architect to understand the design.Work on complete or part of the verification plan, review the same with others in the team.Develop the verification infrastructure and carryout validation.Log/Track and validate defects.B.E/B.Tech 4+ years of experience in Design Verification.or M.E/M.Tech with 2+ years of experience We’re doing work that matters. Help us solve what others can’t.
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