We have an opportunity to impact your career and provide an adventure where you can push the limits of what's possible. The Jisu team in Electronic Trading Technology is looking for an exceptional and experienced FPGA developer to join our ultra-low latency direct market access team. We are a global team with members in New York, London, Athens, Hong Kong, Tokyo, and Mumbai. Our team has developed in-house ultra-low latency connectivity and risk management applications for both external and internal clients. We are a growing the group, expanding beyond equities into supporting markets for other asset classes.

As a Lead Software Engineer at JPMorgan Chase within the Markets Technology Team, you should have the skills and experience developing innovative FPGA based solutions combining both in hardware and software development.

Job responsibilities

Develop complex FPGA solutions for Equities trading with focus on massive throughput and ultra-low latency Interact with users and external vendors for requirements gathering and procurement Partner with internal teams including business, development, quality assurance and operations to deliver reliable and low latency solutions

Required qualifications, capabilities, and skills

Formal training or certification on FPGA architecture design in VHDL/Verilog and 8+ years applied experience High speed/Low latency FPGA design Development of verification strategies and writing complex test benches Excellent understanding of software and hardware interaction Complex system level simulation using modelsim Xilinx/Altera architecture and design experience Working experience with networking protocols including Ethernet/10G, TCP/IP Experience with Unix/Linux based development environment Excellent interpersonal skills Preferred qualifications, capabilities, and skills C++ and Python experience Scripting skills to automate day-to-day development and testing tasks Board design experience Knowledge of intel processor architecture and bus interconnect technologies like PCI-E, QPI Drivers and Memory Management