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Understand/review Design specification and develop verification strategy/Test plan/coverage plan. Development of constrained random verification environments and verification components. Writing tests/sequences/functional coverage/assertions to meet verification goals. Developing c-based test cases for SOC verification.

Required experience

Strong background on functional verification fundamentals, environment planning, test plan generation, environment developmentSystem Verilog experience and experience with UVM based functional verification environment development is required.Good knowledge of verilog/vhdl/C/C++/Perl/Python.Expertise in AMBA protocols. (AXI/AHB/APB).Good knowledge of at least one of the USB/PCIE/Ethernet/DDR/LPDDR or similar protocolsGood handle on using one or more version control softwareGood handle on using one or more load sharing software

Desirable skills and experience

Prior experience with Cadence tools and flows is highly desirable.Familiarity with ARM/CPU architectures is a plus.Experience in developing c-based test cases for SOC verificationSome experience with assembly language programmingGood knowledge of some of the protocols like UART, I2C, SPI, JTAGEmbedded C code development and debugFormal Verification experience

Strong vocabulary, communication, organizational, planning, and presentation skills are essential. Ability to work independently and productively with high quality output and results in a fast paced and dynamic environment. Ability and desire to learn new methodologies, languages, protocols etc. Must be open to constant personal development and growth to meet the evolving demands of the semiconductor industry. Self-motivated and willing take up additional responsibilities to contribute to team’s success.

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