**Job Description** + Develops Electrical Test Plan and Automation Solution for memory systems margin validation. + Validates Memory IO circuit analog performance, electrical signal integrity compliance to industry standard specifications, and system level margin for stable operation and production target prediction. + Review Memory Training for validation and margin optimization. Validate, debugs, and optimizes memory training and circuit analog setting to improve margins and quality. + Conducts and participates in multidisciplinary research in the design, development, testing, validation, and utilization of memory IO and mixed signal architectures inclusive of industry standard datacom applications and custom Intel interfaces. + Provide platform board test requirement and design feedback. + Performs debug to identify root causes and resolves all functional and triage failures for electrical issues. **Qualifications** Min Qualification : + BS, MS degree in Electronic or Computer Science Engineering with at least 5 or more years of experience in related field + Strong problem-solving and analytical skills. Excellent communication and leadership abilities, capable of leading cross-functional debug efforts + Post-silicon system level hardware and software validation techniques and debug skills + Experience in C++, Python or any form of scripting for hardware access or automation Preferred Qualification : + Experience in Memory IP post silicon validation is a plus + Good understanding of DDR5, LPDDR5 memory topology, features and memory PHY circuit architectural analog design knowledge is a plus + Familiar with DRAM initialization, memory training and calibration process + Knowledge in memory analog tuning to improve system level margin + Possess hands on experience in post-silicon circuit electrical characterization activity, be it Bench Design Validation, Signal Integrity Validation, or System Margining Validation + Familiar with validation technique and electrical compliance requirement for high speed memory system + Familiar with DFT usage in Electrical Validation environment + Proficiency in operating hardware measurement equipment and tool, for example: BERT, oscilloscope, sigtest eye diagram tool and etc **Inside this Business Group** The everyday contributions of the Intel Validation Engineering (iVE) team are essential to retaining/regaining Intel's product leadership. We validate, debug, and tune the newest designs and world-changing technologies that enrich the lives of every person on earth. We play a critical role in completing the PRQs of Intel products and in Intel's ability to deliver the annual technology platforms in our roadmap. **Posting Statement** All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. **Benefits** We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits) **Working Model** This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *** Job posting details (such as work model, location or time type) are subject to change.**