Job description:

As a member of the mixed signal team, the candidate will work with senior circuit designers in the design, validation and characterization of mixed signal and analog IP blocks for SOC. The IPs include PLL, DLL, SERDES, high speed IO and data converters, etc. for sub-14nm technologies. The candidate will have exposure to a broad range of circuit and technologies.

Qualification:

Strong fundamental in analog integrated circuit design Good knowledge of digital logic design, including Verilog coding Excellent communication skills Lab skill is a plus Knowledge on signal integrity is a plus MS or PH.D. in electrical engineering Will also consider summer interns