Description The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Senior SoC Integration Design Engineer to continue to innovate on behalf of our customers. We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and reimagined user experience through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at edge. Work hard. Have Fun. Make history. In this role, as a Lead SOC Physical Design Engineer, you will be part of the team developing SoCs to be deployed in a range of Amazon devices. You will integrate industry standard and custom hardware IP and subsystems into SoCs to accelerate applications in machine learning, computer vision and robotics. You will work closely with System Architects, SoC architects, IP developers and SoC RTL design teams to develop SoCs that meets the power, performance and area goals for Amazon devices. You will help define the processes, methods and tools for physical design and implementation of large complex SoCs. Develop chip level and subsystem level netlists integrating IPs and new design. Key job responsibilities · Own all aspects of physical design implementation through synthesis, formal verification, floor planning, bus / pin planning, power domain implementation, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, ECO and sign-off. · Work with RTL/logic designers to drive architectural feasibility studies, explore power-performance-area tradeoffs for physical design closure at the block and Sub System level. . Work closely with third party design and fabrication services to deliver quality first pass silicon that meets all performance, power and area goals. · Contribute to developing physical design methodologies. . Signoff flows including STA, formal verification, EM/IR, reliability and Physical Verification. · Be a highly-valued member of our start-up like team through excellent collaboration and teamwork with other physical design engineers as well as with the RTL/Arch. Teams Basic Qualifications BS + 10yrs or MS + 7yrs in EE/CS 10+ years of experience in all aspects of physical design implementation multiple tape-outs in FINFET technologies such as 5nm/7nm, 14/16nm. Expertise using CAD tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) to block design for synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, and ECO Scripting experience with Tcl, Perl or Python and ability to drive physical design flow automation. Must have good communication and analytical skills. Preferred Qualifications Expertise using CAD tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) develop flows for synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, and ECO Thorough knowledge of device physics, custom/semi-custom implementation techniques. Experience solving physical design challenges across various technologies such as CPU, DDR, PCIe, fabrics etc. Experience in extraction of design parameters, QOR metrics, and analyzing trends. Experience with DFT & DFM flows. Experience leading top level of SoC and all integration issues between IPs and partitions, drive package requirements, resets/clocks and power detection at SoC level Ability to provide mentorship, guidance to junior engineers and be a very effective team player.