Google welcomes people with disabilities. Minimum qualifications: + Bachelor’s degree in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience. + 2 years of experience working in a Power Integrity technical environment, or 1 year of experience with an advanced degree. Preferred qualifications: + MS or PhD in power engineering, signal Integrity or related discipline; understanding of power integrity fundamentals. + 6 years of experience in on-board, on-substrate packages and on-chip power integrity design for FPGA/ASICs/Processors. + Experience with CAD tools such as Ansys HFSS, Q3D, SIwave, Cadence PowerSI, PowerDC, Allegro, APD, CST Microwave Studio, Keysight ADS, and Synopsys Hspice. + Experience with PI validation and correlation at package, die and PCB level. + Knowledge on system power delivery network and switching voltage regulator modeling and simulation. + Knowledge of on-chip inductor, on-die capacitor and on-substrate package inductor technologies. Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Power Integrity Engineer in Technical Infrastructure, you will play a role in the development of one of the computing infrastructures. You will work as part of a team to deliver innovative power integrity solutions for point of load applications. Your objective will be to design, analyze, optimize and implement board, substrate package and chip level power topologies and control for large scale point of load application including ASICs, FPGAs and processors. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible. + Responsible for the on-board power integrity, i.e. PCB stack-up, component placement, bulk/high frequency decoupling caps selection and placement, remote sensing, PCB droop detectors, EM checks, etc. + Design the end to end power delivery from VRM, PCB, package to the Die. Innovate the on-board, on-substrate, and on-chip level power delivery solutions and analyze performance, cost, reliability, and availability trade-offs. + Collaborate with power and EE engineers, and design partners, to drive power integrity (PI), explore design and manufacturability tradeoffs, and ensure that product functions as required. + Partner with power industry leaders to lead evaluation and adoption of technologies, and engage cross-functionally to ensure successful roll-out, testing, and complete validation. + Work cross-functionally with project teams, on system bring up and perform lab design validation, correlation study and root cause debugging. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also https://careers.google.com/eeo/ and https://careers.google.com/jobs/dist/legal/OFCCP_EEO_Post.pdf If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form: https://goo.gl/forms/aBt6Pu71i1kzpLHe2.