Power UPF Methodology Engineer Austin,Texas,United States Hardware Do you have a passion for crafting entirely new solutions? As part of our Digital Design Engineering group, you’ll take imaginative and revolutionary ideas and determine how to turn them into reality! You and your team will apply engineering fundamentals and groundbreaking efforts, bringing forward-thinking ideas to the real world. Join us, and you’ll help design the tools that allow us to bring customers experiences they’ve never before envisioned! You will be part of an exciting silicon design group that is responsible for designing state-of-the-art ASICs. We have an extraordinary opportunity for Power UPF Engineers, who will drive transistor level power ERC sign-off and power intent-UPF implementation & verification on mobile SOCs. **Description** Imagine yourself at the center of our SOC design effort, collaborating with all fields, playing a strategic role of getting functional products to millions of customers quickly. You will have the opportunity to integrate and come-up with new insights, as well as work with a team of hardworking engineers. The main responsibility of this role is to develop and support transistor level power ERC sign-off for digital and mixed signal designs, drive power ERC sign-off at full-chip level, drive UPF implementation and verification for mobile SOCs and make current power sign-off flow more robust and expand power sign-off methodology for next generation mobile products, including: - Drive Mixed signal IP power ERC and power intent verification. - Drive coverage of power intent across static and dynamic checking methodologies. - Define and develop power ERC framework for new projects. - Bring up power intent checking flows on new projects. - Drive power intent & power ERC sign-off for tape-out. - Liaison with CAD and physical design verification team for debugging any power ERC and power intent flow issues. **Minimum Qualifications** + BS and a minimum of 3 years of relevant industry experience **Key Qualifications** **Preferred Qualifications** + We are looking for applicants with experience in ASIC design methodology and an emphasis on power definition. + Experience in ASIC design flows and custom IP design flows. + Familiar with basic circuit & layout fundamentals. + Familiar with Caliber based ERC flows. + Familiar with power intent definition, implementation and verification flows. + Knowledge of scripting languages like, Tcl, Perl and Python. + Familiar with of power analysis and optimization methods. + Familiar with entire RTL2GDS flow (RTL sim (VCS), equivalence, synthesis, P&R, intent checking) + Strong communication skills are a pre-requisite as you will collaborate with a lot of different groups. **Education & Experience** **Additional Requirements** + Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.Learn more about your EEO rights as an applicant. (https://www.eeoc.gov/sites/default/files/2023-06/22-088\_EEOC\_KnowYourRights6.12ScreenRdr.pdf) **Apple Footer** Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant (Opens in a new window) . Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants. United States Department of Labor. Learn more (Opens in a new window) . Apple participates in the E-Verify program in certain locations as required by law. Learn more about the E-Verify program (Opens in a new window) . Apple is committed to working with and providing reasonable accommodation to applicants with physical and mental disabilities. Reasonable Accommodation and Drug Free Workplace policy Learn more (Opens in a new window) . Apple is a drug-free workplace. Reasonable Accommodation and Drug Free Workplace policy Learn more (Opens in a new window) . Apple will consider for employment all qualified applicants with criminal histories in a manner consistent with applicable law. If you’re applying for a position in San Francisco, review the San Francisco Fair Chance Ordinance guidelines (opens in a new window) applicable in your area. It is unlawful in Massachusetts to require or administer a lie detector test as a condition of employment or continued employment. An employer who violates this law shall be subject to criminal penalties and civil liability.