At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. As a Principal Design Engineer you will be responsible for scheduling, designing, developing, and supporting IP models of system level memory such as SDRAM (LPDDR, HBM), NAND Flash (ONFI/QSPI/OSPI), eMMC, SD Card, DFI, and UFS models for use on hardware based verification products. Additional responsibilities include the following: + Updating, maintaining, documenting, and supporting existing system level memory model products. + Perform as individual contributor for RTL design, verification, productizing, and documentation of memory IP. + Interface with internal and external customers to work on diverse problems and solutions related to emulation, simulation, or verification. + Perform as team member toward cross verification of and cross training in memory IP as well as in developing and using lifecycle processes to ensure product quality. + Must be able to analyze customer & vendor protocol requirements and execute on complex projects from requirement to delivery to post-delivery support + Communication & collaboration with peers & internal partners as well as strong individual/independent R&D skills are required. + Regular field AE & external customer interaction and representing Cadence to external customers is required for support of memory models. Must be able to facilitate discussions with AE & customer. + Ability to mentor less experienced engineers &/or participate in cross-functional projects + Must participate in team processes as well as evaluate and recommend process improvements. Required Experience: + The position requires BSEE with at least 7 yrs of industry experience in designing hardware systems OR a MSEE with at least 5 years of experience in designing hardware systems + Must have excellent communication skills with both written and spoken English. + Expert level knowledge of RTL design using languages Verilog/SystemVerilog is required along with experience using RTL verification tools and flows. + Debugging experience. + Experience with team-wide collaboration tools and process. + Drive and ability to schedule workload and plan own tasks effectively. Strongly recommended: + Verification experience using Cadence simulation and/or emulation products is highly desired. Programming experience with scripting languages like Perl, TCL, C-shell is strongly recommended. + Verification experience using UVM test environments is highly desired. + Experience in memory sub-system design and operation is strongly recommended. We’re doing work that matters. Help us solve what others can’t. Additional Jobs (https://cadence.wd1.myworkdayjobs.com/addl\_jobs) Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. 
Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class. Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.